Dynamic voltage and frequency control. Intelligent electric power system with an active-adaptive network: structure, methodological principles, control system Actively adaptive networks

To solve existing problems in the Russian electric power industry, it is necessary to move it to a new qualitative level through the formation of an integral multi-level management system with an increase in the volume of automation and an increase in the reliability of the entire system. This is facilitated by an intelligent energy system with an active-adaptive network, the development of which abroad is called the creation of SMART GRID.

Valeria Lakshevich,

Head of the press service of JSC Intelika (Moscow)

Active-adaptive network

SMART GRID is a term for a smart grid that digitally expands distribution and transportation systems to optimize current operations and open new markets for alternative energy.

The implementation of the concept of “smart grid” (smart grid, in Russia the term “active-adaptive network” is more common) will allow online monitoring and control of the work of all participants in the process of generating, transmitting and consuming electricity, automatically responding promptly to changes in various parameters in energy system and provide electricity with maximum reliability and economic efficiency.

There are many definitions of the concept “smart grid”, among which the following can be distinguished, which most accurately reflect its functionality:

• a network that delivers electricity from producers to consumers using bidirectional digital communications, and controls devices at the consumer to conserve energy, reduce the cost of energy consumption, and increase reliability and transparency (Wikipedia);
• a self-balancing, self-monitoring network that works with all types of generation (gas, coal, solar, wind) and delivers all types of energy (heat, light, hot water) to end consumers with minimal human intervention (Siemens);
• The smart grid digitally expands the distribution and transportation network to optimize current operations and open new markets for alternative energy (IEEE*).

Among the goals of creating an intelligent network, we highlight the following:

• increasing the use of digital and control technologies to ensure the reliability, security and efficiency of the electrical grid;
• dynamic optimization of network operations while ensuring complete information security;
• development and integration of distributed generation, including renewable energy sources;
• demand management. Increasing energy efficiency of consumers;
• use of intelligent technologies to monitor network status and manage the network;
• integration of “smart” metering devices and consumer devices;
• deployment and integration of energy storage and peak shaving technologies;
• providing consumers with timely information and control capabilities;
• development of standards for the interaction of “smart” devices and equipment connected to the network, including the network management infrastructure (Plug&Play);
• Identifying and reducing unreasonable and unnecessary barriers to the development of smart grid technologies, practices and services.

Attitude to the concept of energy saving

The “smart grid” concept is extremely popular in many countries around the world and is designed not only for grid companies themselves, but also for consumers, generation and distribution companies. At the same time, smart metering is a necessary condition for implementing the task of increasing the efficiency of the UES of Russia and the first step towards building a smart energy system.

Of course, in Russia there are already leaders in energy saving issues who have achieved real results in saving fuel and energy resources. As a rule, these are commercial industrial enterprises that are certainly interested in reducing the energy intensity of production, as this increases their competitiveness and profits. They approach the issue systematically and have been implementing comprehensive programs for a long time, including both the modernization of basic production equipment and increasing the energy efficiency of buildings and structures.

Things are worse in government organizations, because, without facing the need to compete in the market, they passively carry out the tasks of higher authorities. Taking into account the colossal property complex owned by the state, it makes sense to focus on the development of energy service contracts in this sector and on attracting private companies to reduce energy costs.

As for the population, it is very passive, since people simply cannot see how energy costs relate to their behavior. It is necessary to introduce intelligent technologies for metering electricity and other resources, providing the opportunity for private consumers to form their consumption profile. Having the opportunity to choose a flexible tariff, the consumer will be able to save, almost only by changing their habits.

The use of smart metering devices

Let us dwell in more detail on the use of “smart” metering devices to implement the large-scale task of building a smart network. If in Russia such projects are only gaining momentum, given certain Federal law No. 261-FZ on energy saving, the deadline for the mandatory installation of metering devices, then in the world the process has long been launched and similar initiatives number in tens and hundreds.

For example, the Canadian government passed a law in 2006 (Energy Conservation Responsibility Act), which requires the installation of “smart” meters in every home and office by 2010 and is successfully moving towards this goal. Ontario's public grid and distribution company, Hydro One, has developed and is implementing a major smart metering initiative. By the end of 2010, this initiative will reach approximately 1.3 million customers in the company's service territory. This project received the "Best AMR Initiative in North America" ​​award.

The EU countries set themselves the task of reducing energy consumption by 20% by 2020 and are implementing the necessary projects for this. For example, back in 2006, Enel, the largest Italian energy company, completed a project to equip 32 million of its own consumers with smart meters. Swedish energy companies have already supplied 100% of electricity consumers with such devices.

In Russia today there is a real problem that residential and commercial buildings waste a lot of electricity, and the organizations involved in the operation of such buildings do not know how much electricity is consumed at any given time. This is because existing networks are not equipped with feedback systems and digital controllers that could help with energy distribution and saving.

This problem gives rise to the need to equip existing distribution networks at the borders with consumers with metering devices connected into a single information network and allowing for optimal consumption of energy resources.

A possible solution could be the use, for example, of metering devices with an advance payment system for energy resources.

U classical scheme There are many negative aspects when paying for consumed energy resources. In our opinion, the key problem is the growing operating costs, which are included in the tariff, which leads to an increase in the cost of 1 kWh for the end consumer. An increase in the cost of 1 kWh leads to an increase in the average bill, which, in turn, affects the solvency of low-income segments of the population. This, of course, entails an increase in accounts receivable, as well as an increase in the cost of preventive measures to combat it (selling debts to collectors, additional information to consumers by calling, printing reminder letters, debt receipts, and so on). In addition to such inevitable operating expenses as rent of premises, payroll and taxes, there is a group of costs that can be significantly reduced:

• cost of servicing loans intended to cover cash gaps;
• recurring costs for printing, converting and delivering invoices;
• maintaining a staff of inspectors/inspectors who carry out control walks and manually take readings from metering devices;
• expenses associated with the collection of receivables and the conduct of claims work in the event that it is impossible to collect debts on our own.

A way out of the situation may be the introduction of solutions based on the principle of advance payments using smart cards, such as, for example, Intelica Meter-To-Cash. The process of interaction between the sales company and the subscriber is extremely simplified and is built according to the following algorithm:

• the subscriber deposits funds onto the smart card using a self-service terminal/ATM or an energy sales company operator;
• returning home, the subscriber inserts the card for 2 seconds. into the metering device. In this case, payment and tariff data are recorded in the device’s memory;
• as electricity is consumed, the meter writes off funds in accordance with the subscriber’s tariff;
• when a certain level of funds is reached (can be set individually for each subscriber), the meter automatically informs the subscriber with sound signals about the need to replenish the balance;
• If the funds in the consumer's account have run out, it is possible to supply electricity on credit. The loan amount can also be set individually for each subscriber. When the credit is exhausted, the device automatically turns off until funds are deposited;
• After replenishing the balance, the device returns to normal operation.

In addition to automatic shutdown, there is a power limitation mode. When this mode is activated, the device will produce short-term shutdowns when the set power threshold is exceeded.

Benefits of a Smart Grid

The implementation of such a system allows the consumer to see how his behavior affects the cost of electricity. Such intelligent electricity metering technologies provide the opportunity for private consumers to create their own consumption profile. This, in turn, strengthens the “energy consciousness” of the consumer, who, pursuing his own savings goals, gradually becomes an active link in the energy system. Sales companies, in turn, completely solve the problem of non-payments in the household sector.

The bar set by the new state program for energy saving and energy efficiency, adopted in October 2010 and envisaging a reduction in the energy intensity of GDP by at least 13.5% by 2020, is very high. To accomplish such a complex task, an integrated approach is required, covering all subjects of the electricity market: producers (generators), networks, sales companies and, of course, consumers, and using technologies and processes that adequately take into account their interests.

________________________________________________________________________

* Institute of Electrical and Electronics Engineers - Institute of Electrical and Electronics Engineers, an international non-profit association of specialists in the field of technology.

The inventions relate to integrated circuits and can be used for dynamic control of voltage and frequency in integrated circuits. The technical result is to ensure the correct operation of the integrated circuit. The device includes a logic circuit, a local power management device, and a self-calibration module configured to repeat the test of the logic circuit in the integrated circuit at correspondingly lower supply voltages until the test fails. The lowest supply voltage value at which the test passes is used to generate the requested supply voltage value for the integrated circuit. 2 n. and 12 salary f-ly, 13 ill.

BACKGROUND OF THE ART

FIELD OF TECHNOLOGY TO WHICH THE INVENTION RELATES

This invention relates to integrated circuits and, more particularly, to dynamic control of voltage and frequency in an integrated circuit.

DESCRIPTION OF THE PRIOR ART

As the number of transistors on a single integrated circuit "die" increases, and as the operating frequency of integrated circuits increases, the importance of controlling the power consumed by the integrated circuit continues to grow. If power consumption is not controlled, meeting the thermal specifications for an integrated circuit (eg, providing the components required to sufficiently cool the integrated circuit during operation to remain within the operating temperatures of the integrated circuit) may be prohibitively expensive or even unfeasible. Additionally, in some applications, such as battery-powered devices, managing power consumption on the IC may be key to achieving acceptable battery life.

The power consumption in an integrated circuit is related to the supply voltage provided to the integrated circuit. For example, many digital logic circuits represent a binary one and a binary zero as supply voltage and ground voltage, respectively (or vice versa). As discrete logic performs calculations during operation, the signals often transition completely from one voltage to another. Thus, the power consumed in an integrated circuit depends on the magnitude of the supply voltage relative to the ground voltage. Reducing the supply voltage generally results in a reduction in power consumption, but also affects the speed at which digital circuits operate, and thus may cause improper operation at a given operating frequency (that is, the frequency at which the discrete logic in the integrated circuit is clocked) or may reduce performance.

Additionally, as transistor sizes continue to shrink, leakage currents, which occur when a transistor is not actively conducting current, have become a large component of power consumed in an integrated circuit. The amount of leakage current occurring in a given transistor generally increases linearly with increasing supply voltage. In addition, with each new semiconductor production of functional units (which reduces the size of the transistors), the leakage current increases more than the active (ON state) currents. Thus, as more advanced functional units are used, leakage current becomes more and more of a problem.

Thus, power consumption in an integrated circuit can be controlled by reducing the supply voltage of the integrated circuit, but the result may be incorrect operation if the supply voltage is reduced too much. The amount of supply voltage at which improper operation occurs for a given operating frequency varies from instance to instance for a given integrated circuit device. For example, changes in the manufacturing process used to produce an integrated circuit, and operating temperature IC chips can influence the supply voltage value at which incorrect operation occurs. Accordingly, attempts to control power consumption through supply voltage have been limited to supply voltage values ​​that guarantee correct operation at a given frequency for all permissible manufacturing process variations and all permissible operating temperatures. Typically, the supply voltage for a given frequency is statically specified in the specification of the integrated circuit.

SUMMARY OF THE INVENTION

In an embodiment, the integrated circuit includes a logic circuit, a local power management device coupled to the logic circuit, and a self-calibration module. The local power management device is configured to transmit an indication of the requested supply voltage value to the external power source. The self-calibration module is configured to perform a logic circuit test and repeat the test at a correspondingly lower requested supply voltage value until the test fails. The lowest requested supply voltage value at which the test passes is used to generate the required supply voltage value for operation of the integrated circuit.

In an embodiment, the method comprises repeating a logic circuit test by the self-calibration module at correspondingly lower required supply voltage values ​​for the integrated circuit chip that includes the logic circuit and the self-calibration module until the test fails. The method further comprises a self-calibration module that determines the lowest required supply voltage value at which the test is successful. Another method further comprises a self-calibration module that selects the lowest requested supply voltage value to generate the requested supply voltage value for operation of the integrated circuit.

In an embodiment, the integrated circuit includes a plurality of logic gates physically distributed over a portion of the integrated circuit that is occupied by a logic circuit that implements the operation of the integrated circuit, where the plurality of logic gates are connected in series; and the measurement module is connected to the first gate in the series connection and the last gate in the series connection. A measurement module configured to trigger a logical transition at the first gate and measure the time when a corresponding transition is detected at the last gate. The measured time is compared with a preset time to adjust the supply voltage of the integrated circuit. In some embodiments, a predetermined time may be determined during a self-calibration procedure. In some embodiments, the predetermined time may be measured as the number of clock cycles it takes for a pulse to pass through all logic gates connected in series.

In an embodiment, the method comprises a measurement module that triggers a logic transition to a first gate in a series connection of a plurality of logic gates that are physically distributed over a portion of the integrated circuit that is occupied by a logic circuit that implements the operation of the integrated circuit; and a measurement unit that measures the time when a corresponding transition is detected in the last gate, and wherein the measured time is compared with a predetermined time to adjust the supply voltage of the integrated circuit.

BRIEF DESCRIPTION OF THE DRAWINGS

Subsequent detailed description refers to the accompanying drawings, which will now be briefly described.

FIG. 1 is a block diagram of one embodiment of an integrated circuit.

FIG. 2 is a flowchart that depicts one embodiment of a test of the integrated circuit shown in FIG. 1.

FIG. 3 is a flowchart that depicts the operation of one embodiment of the self-calibration module shown in FIG. 1.

FIG. 4 is a flowchart that depicts the operation of one embodiment of the integrated circuit shown in FIG. 1 in changing the operating frequency of the integrated circuit.

FIG. 5 is a flowchart that depicts, for one embodiment, performing self-calibration in response to various events.

FIG. 6 is a block diagram of another embodiment of an integrated circuit.

FIG. 7 is a flowchart that depicts one embodiment of the test of the integrated circuit shown in FIG. 6.

FIG. 8 is a flowchart that depicts the operation of one embodiment of an integrated circuit upon a supply voltage demand.

FIG. 9 is a flowchart that depicts the operation of one embodiment of the integrated circuit shown in FIG. 6 in changing the operating frequency of the integrated circuit.

FIG. 10 is a flowchart that depicts another embodiment of the test of the integrated circuit shown in FIG. 6.

FIG. 11 is a flowchart that depicts the operation of one embodiment of the speed/temperature compensation module shown in FIG. 6. FIG.

FIG. 12 is a graphical representation of the number of instances that can operate at different supply voltages and test voltages that can be used in one embodiment of integrated circuit testing.

FIG. 13 is a graphical representation of the number of instances that can operate at different supply voltages and test voltages that can be used in another embodiment of integrated circuit testing.

Although the invention is susceptible to various modifications and alternative forms, specific embodiments thereof are shown by way of example in the drawings and will be described in detail herein. It should be understood, however, that the drawings and detailed description thereof do not limit the invention to the particular form disclosed, but rather, it is intended to cover all modifications, equivalents and variations falling within the spirit and scope of the present invention as set forth in the appended claims. Headings used herein are for organizational purposes only and are not intended to limit the scope of the description. Throughout this application, the word “may” is used in a permissive sense (ie, having the potential to do something) rather than in a mandatory sense (ie, meaning necessary). Likewise, the words “include,” “including,” and “includes” mean inclusion rather than limitation.

Various modules, circuits, or other components may be described as being "capable" of performing a task or tasks. In such contexts, "capable of" is a broad reading of the design, generally meaning "has electrical circuitry that" performs a task or tasks during operation. Thus, the module/circuitry/component may be configured to perform a task even when the module/circuitry/component is not currently turned on. In general, the electrical circuitry that forms the structure corresponding to "capable" may include hardware circuitry and/or stored executable program instructions for implementing the operation. The memory may include short-term memory such as static or dynamic random access memory and/or non-volatile memory such as optical or magnetic disk storage, flash memory, programmable read-only memory (ROM), etc. Likewise, various modules/circuits/components may be described as performing a task or tasks for convenience in the description. Such descriptions should be interpreted to include the phrase “capable of being performed.” A description of a module/circuitry/component that is configured to perform one or more tasks does not expressly imply an interpretation of that module/circuitry/component under 35 U.S.C. paragraph six. § 112 USC.

DETAILED DESCRIPTION OF EMBODIMENT OPTIONS

Turning now to FIG. 1, a block diagram of one embodiment of an integrated circuit 10 coupled to an external power management unit (PMU)/power supply 12 is shown. In the illustrated embodiment, the integrated circuit 10 includes a logic circuit 14, a self-calibration module 16, a local power management device 18 (which may include a self-calibration table 20), and a frequency/voltage (F/V) table 22. Self-calibration module 16 and F/V table 22 are coupled to local power management unit 18, which is coupled to PMU/power supply 12 to provide an indication of the requested supply voltage value (VDD request). The PMU/power supply 12 is coupled to the integrated circuit 10 to provide a supply voltage (VDD) of the required value. The components depicted within the integrated circuit 10 are integrated onto a single semiconductor substrate or chip.

Typically, self-calibration module 16 contains electrical control circuitry along with a test to be performed by logic circuitry 14. The test may be designed to test known "critical" timing paths in logic circuitry 14. The critical timing path may be a path through electrical circuitry that is is expected to exhibit the highest latency (compared to other timing routes) from an input transition to the corresponding output transition, and thus will be the route that limits the operating frequency at which logic circuit 14 will operate correctly. The nature of the test may vary depending on the definition of the logic circuit 14. For example, if the logic circuit 14 includes one or more processor cores, the test may contain a program to be executed by the processor core(s), along with the expected result of the program (e.g. signature). If logic circuit 14 includes standard function circuitry, the test may include input signal values ​​and expected output signal values. IN various options an implementation may include a combination of signal values ​​and program instructions.

Electrical circuitry in self-calibration module 16 may be configured to perform a test on logic circuit 14 (eg, providing instructions to the processor core(s) to execute and/or driving signals using input signal values). The electrical circuitry in the self-calibration module may also be configured to verify the result by comparison with the expected value. The self-calibration module 16 may be configured to repeat the test and communicate with the local power management device 18 to request lower supply voltage values ​​for each repeat until an incorrect repeat result is detected. The lowest supply voltage value for which a valid test result is detected may be provided as the requested supply voltage value (or some allowance may be added to the lowest supply voltage value to obtain the value that will be requested). The self-calibration module 16 may repeat the test for each possible operating frequency or may perform the test for a given operating frequency in response to the first actual request for a given operating frequency for the integrated circuit 10 (eg, by software).

When using the self-calibration module 20, in some embodiments, a smaller allowance may be used since the self-calibration occurs with the integrated circuit 10 installed in the specific device in which it will be used (and thus some factors that are taken into account by the allowance, such as variations in power supply 12, board design, mounting of the integrated circuit 10 in the package, etc. are generally eliminated). Additionally, in some embodiments, rather than testing for the lowest supply voltage during the factory test phase, lower supply voltages may be tested at that time, and thus the factory test time can be reduced. Additionally, in some embodiments, the self-calibration module 16 may be activated at any time, thereby automatically making adjustments to account for the effects of aging on the integrated circuit 10.

In one embodiment, the local power management device 18 may store the resulting power voltage values ​​provided by the self-calibration module 16 in a self-calibration table 20 . Self-calibration table 20 can be RAM, synchronous memories such as registers, or any other short-term memory. According to another embodiment, non-volatile memory such as programmable ROM, flash memory, etc. may be used. Thereafter, if an entry for a given operating frequency is detected in the self-calibration table 20, the supply voltage value recorded in the entry may be requested by the local power management device 18.

The F/V table 22 may contain multiple entries, each containing a corresponding operating frequency for the integrated circuit 10 and a corresponding supply voltage value for that frequency. The operating frequency may be the frequency of the clock generator provided with the synchronous memories in logic circuit 14. There may be a range of frequencies at which the integrated circuit 10 can operate (and switching between frequencies within that range may be supported by the integrated circuit 10, for example to allow control power supply, temperature control, etc.). The F/V table 22 may be a static table recorded during a factory test of the integrated circuit 10 (eg, before mounting the integrated circuit in a package, such as during a wafer test). In other embodiments, the test may be performed at any time prior to the sale of the integrated circuit chip 10 for installation in a device, or prior to installation of the integrated circuit chip 10 in such a device; in other embodiments, the F/V table 22 may be recorded during self-calibration, which may be performed before the first use of the device, including the integrated circuit 10. Thus, the supply voltage value determined for each frequency in the F/V table 22 may have a corresponding significant voltage safety interval to ensure correct operation in the case where electrical characteristics packages vary the magnitude of the voltage to account for changing temperatures (for example, the test may be performed at a controlled temperature and the operating temperature may be higher or lower than that temperature), to account for the effects of aging on the integrated circuit over its expected life, etc. .d.

The local power management device 18 includes electrical circuitry that is configured to request a supply voltage value from an external power source (eg, PMU/power supply 12). As mentioned previously, if an entry for a given operating frequency is detected in the self-calibration table 20, the local power management device 18 may query the supply voltage value recorded in that entry. If no entry is found in the self-calibration table 20, the local power management device 18 can read the F/V table 22 for a given operating frequency and can request this supply voltage value from the PMU/power supply 12 (VDD request in FIG. 1). The request can be submitted in any desired form. For example, a request may contain multiple bits, and different supply voltage values ​​within the range of supported values ​​are assigned a different multiple-bit code.

The local power management device 18 may also be configured to control changes in operating frequencies. For example, local power management device 18 may include a register or other means into which software can write to select a new operating frequency. The local power management device 18 may detect the fact of the write and may control the transition from the current operating frequency to the newly requested operating frequency. The transition may include a change in the requested supply voltage, a change in the operation of the timing circuitry (eg, resynchronization of the phase-locked loop (PLL) that generates the clock pulses in the integrated circuit 10, etc.), etc. Thus, in one embodiment, the details of the transition can be separated from the software, which can simply request a new frequency and continue running (eg, without even checking to see if the transition has completed).

Table 22 F/V can be written in any desired form. For example, each entry in the table may contain fuses that can be selectively blown to permanently store in the entry a reading of the desired voltage value (eg, encoded as a plurality of bits in the entry). In other embodiments, any other non-volatile storage device may be used. The F/V table 22 may include non-volatile memory that can be written to by updating the firmware of the device that includes the integrated circuit chip 10.

In some embodiments, the test that is performed by self-calibration module 16 may be programmable and updateable. Such embodiments may allow the test to change as more data becomes available. For example, a route different from the previously identified critical routes may dominate or greatly influence the supply voltage at which the integrated circuit 10 operates correctly. The test can be updated to account for a newly discovered critical route. Moreover, in some embodiments, the test may be updated to include a more appropriate program to run during the test.

Typically, logic circuit 14 may include circuitry that implements the action for which integrated circuit chip 10 is designed. For example, if the design includes one or more processors, logic circuit 14 may include circuitry that implements the actions of the processor (e.g. , calling the command, decoding, executing and writing the result). Processors may include general-purpose processors and/or graphics processors in various embodiments. If the design includes a peripheral interface interface, then the logic circuit 14 may include electrical circuitry that implements the operation of the interface. If the design contains other communication capabilities, such as packet interfaces, network interfaces, etc., the logic circuit 14 may include electrical circuitry that implements the corresponding capabilities. In general, the integrated circuit 10 may be designed to provide any set of actions. Typically, logic circuit 14 may comprise any combination of one or more of the following: a memory array, combinatorial logic, state machines, flip-flops, registers, other synchronous memories, application-specific logic circuits, etc.

Typically, the PMU/power supply 12 may comprise any electrical circuitry that is capable of generating the magnitude of the supply voltage specified in the input voltage request. For example, the electrical circuit may include one or more voltage regulators or other power sources. The PMU/power supply 12 may also include power management circuitry for the system (which includes the integrated circuit 10) as a whole.

Although the discussion above referred to requesting a supply voltage value and the PMU/power supply 12 providing the requested voltage value, the discussion did not imply that there is only one voltage requested/supplied. There may be multiple supply voltages that are requested and supplied at any given time. For example, there may be separate supply voltages for the combinatorial logic circuitry and for the memory circuitry in logic circuit 14. There may be multiple voltage regions within the integrated circuit 10 that can be turned on and off separately, and each region may include a separate request . Local power management device 18 may be powered separately from logic circuit 14. Any plurality of one or more power supply voltages may be requested and supplied.

The supply voltage value was mentioned above as the requested value, and the supply voltage of the requested value as the supplied one. The magnitude of the supply voltage may be measured relative to a reference voltage (eg, IC 10 ground voltage, sometimes referred to as VSS). For convenience of the following description, voltages may be referred to as being greater or less than other voltages. Similarly, this document may refer to a voltage measurement, in which case it is meant that it is a voltage value greater than (or less than) another voltage or what is being measured.

Turning now to FIG. 2, a flowchart is shown that depicts one embodiment of testing the integrated circuit chip 10 shown in FIG. 1 prior to mounting the integrated circuit chip in the package. The blocks shown in FIG. 2 may be performed on a test facility (eg, a wafer tester) during production of the integrated circuit 10.

The test may begin by testing to approximate the characteristics of the integrated circuit 10 (block 30), using various measurements to evaluate whether the integrated circuit is relatively fast, relatively slow, etc. For example, in one embodiment, the approximate characterization may include testing the input current of the integrated circuit 10 while the integrated circuit 10 is in steady state (often referred to as steady state current excursion testing (“Iddq” testing)). Higher Iddq measurements may indicate higher leakage (eg a "faster" process). Lower Iddq measurements may indicate lower leakage (eg a "slower" process). Iddq testing may be performed, for example, with the maximum supply voltage allowed for the integrated circuit 10. From the rough specification (and from previous testing results of instances of the integrated circuit 10), a relatively small set of test supply voltages may be selected. That is, based on supply voltages that provide reliable operation on previous instances having similar approximate characteristics, only a small number of test voltages can be selected (block 32). For example, in one embodiment, a set of three test voltages may be selected. FIG. 12 is a graphical representation of the distribution of instances from the fast process (left side of FIG. 12) to the slow process (right side of FIG. 12). As depicted in FIG. 12, the test voltages for one example may be V1, V2 and V3.

The test setup may turn on power to the integrated circuit 10 (eg, at the highest of the test voltages) and may set a test frequency (one of the frequencies at which the integrated circuit 10 is supported to operate - block 34). The test apparatus may execute one or more test sequences on the integrated circuit 10 for each voltage of a plurality of test voltages (block 36) and may select the lowest test voltage for which all test sequences pass (that is, the correct result is achieved for each sequence - block 38). If there are additional test frequencies (for example, additional supported operating frequencies for the integrated circuit 10 that have not yet been tested - branch block 40, branch "yes"), then the next frequency (blocks 34, 36 and 38) can be selected and tested. The set of test voltages may contain a different test voltage for each supported operating frequency, or may be selected such that for each supported operating frequency at least one supply voltage is expected to pass the tests. Once the test frequencies are exhausted (branch block 40, branch "no"), the test apparatus can record the frequencies and voltage values ​​in the F/V table 22 (block 42). For example, fuses can be melted to display supported frequencies and corresponding supply voltage values.

Since the number of test voltages is limited, the testing process may not determine the lowest supply voltage that causes correct operation of a particular instance of integrated circuit 10. However, time in the test setup may be limited, which may be important in general and especially if large amounts of time are expected. integrated circuit production volumes 10.

Turning now to FIG. 3, the flow diagram depicts the operation of one embodiment of self-calibration module 16 (and local power management device 18) to perform self-calibration. Self-calibration can be performed repeatedly, as discussed in more detail below. Although the blocks are shown in a specific order for ease of understanding, other arrangements may be used. The blocks may be executed in parallel in a combinatorial logic circuit in the self-calibration module 16 and/or the local power management device 18 . Blocks, combinations of blocks, and/or the flowchart as a whole can be executed in a pipeline manner over multiple clock cycles.

Self-calibration module 16 may communicate with local power management device 18 to indicate that a self-calibration process is in progress. According to another embodiment, local power management device 18 may initiate a self-calibration process and may thus know that a self-calibration process is in progress. In either case, the local power management device 18 may request a supply voltage value, which is provided in the F/V table 22 for the test frequency (block 50). Each operating frequency that is supported by the integrated circuit 10 may be a test frequency, for example, starting with the lowest frequency. Local power management device 18 may set the test frequency (block 52) and may wait for the integrated circuit to stabilize at the test frequency (e.g., phase-locked loop (PLL) clock time and/or settling time for voltage from PMU/power supply 12 ). The self-calibration module 16 may perform a self-calibration test (block 54) and determine whether the logic circuit 14 produces the correct result (pass) or not (failure) (branch block 56). If the test passes (branch block 56, branch "yes"), self-calibration module 16 can report this to local power management device 18, which can request the next lower supply voltage (block 58), and the test can be performed again (blocks 54 and 56). The test can be repeated until the test is found unsuccessful result(blocks 54, 56 and 58). Once a failure is detected (branch block 56, branch no), local power management device 18 may record the value of the lowest successful supply voltage in self-calibration table 20 (block 60). In some embodiments, an allowance may be added to the lowest passing supply voltage to obtain a voltage value that will be recorded in the self-calibration table. According to another embodiment, the allowance may be added when the supply voltage is requested. If there are additional test frequencies at which self-calibration needs to be performed (Branch block 62, branch "yes"), then the self-calibration process returns to block 50 for the next frequency. Otherwise (branch block 62, branch "no") the self-calibration process ends.

Turning now to FIG. 4, a flowchart is shown that depicts the operation of one embodiment of local power management device 18 in response to a request to change the operating frequency (for example, from software running on integrated circuit chip 10 or elsewhere in system that contains an integrated circuit 10). Although the blocks are shown in a specific order for ease of understanding, other arrangements may be used. The blocks may be executed in parallel in a combinatorial logic circuit in the local power management device 18. Blocks, combinations of blocks, and/or the flowchart as a whole can be executed in a pipeline manner over multiple clock cycles.

Local power management device 18 may check self-calibration table 20 for an entry corresponding to the new (requested) operating frequency (branch block 70). If the entry is found (branch block 70, branch "yes"), the local power management device 18 may request a supply voltage of the value indicated in the self-calibration table 20 (block 72). Local power management device 18 may set the new operating frequency (block 74) and may, in some cases depending on the implementation, wait for the circuitry to lock onto the new operating frequency (block 76). On the other hand, if there is no entry in the self-calibration table 20 for the requested frequency (branch block 70, branch "no"), then the local power management device 18 can determine whether self-calibration should be performed for the desired frequency (branch block 78). For example, the flowchart of FIG. 3 may be executed with the requested frequency as the only test frequency. Factors that may influence whether to perform self-calibration during a frequency change may include the current workload of the logic circuit 14, the general system environment (eg, temperature, remaining battery life, etc.). For example, if logic circuit 14 contains many processor cores and one of the cores is inactive, self-calibration may be performed on the inactive processor core. If the system is running on battery power and the remaining battery life is short, performing self-calibration may consume more battery power than desired.

If local power management device 18 determines that self-calibration should be performed (block 78, branch yes), then local power management device 18 may call self-calibration module 16 to perform self-calibration (block 80). The local power management device 18 may then request the supply voltage indicated in the self-calibration table 20 (after completion of the self-calibration - block 72), set a new operating frequency (block 74), and in some cases wait for the frequency to lock (block 76).

If local power management device 18 determines that self-calibration should not be performed (branch block 78, branch "no"), then local power management device 18 may read F/V table 22 to obtain a supply voltage value and may query that supply voltage value. (block 82). Local power management device 18 may set a new frequency, and in some cases wait for the frequency to lock (block 74 and 76).

In the embodiment of FIG. 4, self-calibration may be performed in response to a requested operating frequency for which an entry in the self-calibration table 20 is not found. In addition to or instead of this operation, self-calibration may be invoked at one or more other times (eg, as shown in the flowchart of FIG. 5 for one embodiment). The flowchart shown in FIG. 5 may be implemented using hardware, software, and/or a combination thereof.

If the system that contains the integrated circuit chip 10 is booted for the first time (eg, by a customer who purchased the system - branch block 90, branch "yes"), then the integrated circuit chip 10 may perform a self-calibration (block 92). Typically, system booting can refer to turning on the system and preparing the system to begin operation. Determining that boot is the first boot of the system can be done in a variety of ways. For example, there may be a flag stored in non-volatile memory on the system that may indicate whether the system is booting for the first time. The flag may be checked by bootstrap code on the system, and the state of the flag may be changed at the end of the bootstrap code if the bootstrap is the first boot, so that subsequent bootstrap cannot be recognized as the first boot. For example, a flag may be a bit that is not initially set, but is set after the first boot (or vice versa). In some embodiments, a full system reset (eg, a "hard" reset initiated by the user activating one or more device inputs) may clear the "first boot" flag and force self-calibration on the next boot. In some embodiments, such an operation may improve the functionality of the device. For example, if a user initiates a "hard" reset because the device is "unresponsive" or otherwise malfunctioning, self-calibration may partially resolve the error if it is an error due to improper functioning of the IC 10 (e.g., due to that the self-calibration value of the supply voltage is too low). Additionally, if the device is connected to a network (such as the Internet), an updated calibration program or procedure can be automatically downloaded to the device from the device manufacturer. Self-calibration may be performed in response to an update.

Alternatively or in addition, the system may determine that this is the first time a given workload is running (Block 94, branch "yes"), and may self-calibrate in response (Block 92). Deciding that this is the first time a given workload is running can be implemented in a variety of ways (eg, a flag for each workload in the non-volatile storage device, similar to the discussion above regarding the first boot). Detection of different workloads can be used, for example, in a system in which the workloads vary significantly. For example, the system may be a mobile device that can function as a mobile phone, an audio player, a web browser, and can perform various other computing tasks. Workloads may vary widely and may require different amounts of performance from the integrated circuit chip 10. Accordingly, self-calibration for each workload may result in additional power savings (e.g., a smaller load may result in a lower operating temperature, which may allow a lower supply voltages than would allow higher workloads).

In yet another embodiment or addition, the system may determine that its age has increased by a certain amount (Block 96, "yes" branch) and may self-calibrate in response (Block 92). Performing self-calibration in response to aging of the integrated circuit chip 10 (and/or a device that includes the integrated circuit chip 10) may adjust the required supply voltage values ​​for the integrated circuit chip 10 to compensate for the effects of the chip aging process or other aging effects. Thus, there is no need to add an allowance to the required supply voltage to account for aging effects (since they are already taken into account during recalibration during the aging process of the integrated circuit 10). The age of the integrated circuit 10 can be measured in a variety of ways. For example, age may be measured from the first boot date based on calendar time. Age can be measured by the operating time from the first boot. Age can be measured in units of time or number of ticks, as desired. In other embodiments, age may also be measured relative to the date of manufacture. In any case, self-calibration can be performed many times for different ages (for example, once every 6 months, once a year, etc.). In other cases, self-calibration can be performed dynamically while the system is in operation, which can help compensate for temperature effects. Any desired set of self-calibration calls may be implemented in various embodiments.

Referring now to FIG. 6, a block diagram of another embodiment of the integrated circuit 10 and PMU/power supply 12 is shown. Similar to the embodiment of FIG. 1, the embodiment of the integrated circuit 10 of FIG. 6 includes a logic circuit 14 and a local power management device 18. Some embodiments may include a self-calibration module 16 and a self-calibration table 20, while other embodiments may be without this functionality. In the embodiment of FIG. 6, the F/V table 22 of FIG. 1 is replaced by an F/V/N table 102 associated with the local power management device 18. The F/V/N table 102 may contain entries storing frequency and corresponding supply voltage values, similar to the F/V table 22. In addition, recordings may store a latency measurement (N), described in more detail below. As further depicted in the embodiment of FIG. 6, the integrated circuit 10 may include a measurement module 100 and logic gates 104A-104H coupled in a series connection. The input of logic gate(s) 104A is coupled to measurement module 100, and the output of logic gate(s) 104H is also coupled to measurement module 100. In addition, flip-flop 106 stores the expected delay measurement (N), and flip-flop 108 stores a counter value (Ctr). Both flip-flops 106 and 108 are coupled to measurement module 100. In other embodiments, flip-flops 106 and 108 may be any synchronous storage devices.

The measurement module 100 may be configured to measure the propagation delay of a logical transition through serial connection valves 104A-104H. The gates 104A-104H may be of the same design as the various logic gates in logic circuit 14. Accordingly, the propagation delay through the gates 104A-104H must be proportional to the logic gates in logic circuit 14. By measuring the propagation delay and comparing it with a predetermined delay, the influence of various factors on the operation of the logic circuit 14 can be taken into account. For example, the effects of operating temperature, aging, etc. can be detected. when measuring the propagation delay and comparing it with a predetermined value.

Propagation delay can be measured in any desired units (eg nanoseconds, clock cycles, etc.). In one embodiment, the propagation delay is measured in units of clocks of the current operating frequency of the clock provided in logic circuit 14. Accordingly, measurement module 100 may trigger a logic transition (e.g., a zero-to-one or a one-to-zero transition) into the daisy chain input of gates 104A. -104H (ie, the input of gates 104A in FIG. 6) and can count clock cycles until a corresponding transition is detected at the serial connection pin (ie, the output of gates 104H in FIG. 6). In one embodiment, a pulse may be transmitted containing two logical transitions (eg, zero to one and back to zero). The Ctr counter in flip-flop 108 may be cleared when a logical transition is triggered, and may be incremented each clock cycle until a corresponding transition is detected. The flip-flop 106 may store a predetermined number (N) of clock cycles that is expected to pass if the supply voltage provides a delay that maintains the current operating frequency. If the measured number of clock cycles is greater than a predetermined number N, then the supply voltage can be increased to reduce latency. If the measured number of clock cycles is less than a predetermined number N, then the supply voltage can be reduced to increase latency (and consume less power).

The number of gates in a series connection may be significantly greater than the number of gate lags that can operate within a clock cycle provided by the logic circuit 14. For example, the number of gates connected in series may be approximately 100 times the number of gate lags per clock cycle. Thus, if 14 gate delays are available per clock, then approximately 1400 gates can be sequentially connected in gates 104A-104H. Using a large number of gates can improve the correspondence of the measured delay to the circuit delay actually occurring in logic circuit 14. Moreover, since the present embodiment counts the delay in units of clock cycles, a large number of gates can reduce the measurement error that occurs due to clock granularity. For example, when the number is 100 times larger number valve delays per clock cycle, the error in the delay for one full cycle (the maximum possible error) is only 1% of the measured value. Although this embodiment uses the number 100, other embodiments may use larger or smaller numbers (eg, 200, 500, 100, 50, etc.).

A predetermined number N can be measured during factory testing of the integrated circuit. It is generally expected that the predetermined number N will be close to a multiple of the number of gate delays that was used to create the series connection of gates (for example, 100 in the above example), but may differ slightly from this number. In one embodiment, a predetermined number N may be stored in the F/V/N table 102 along with a static supply voltage value for a given operating frequency. In various embodiments, there may be one number N stored in a table, or there may be one number N for each operating frequency (in the entry corresponding to that operating frequency).

The gates 104A-104H may be physically distributed throughout the portion of the integrated circuit 10 that is occupied by the logic circuit 14. Accordingly, the propagation delay may take into account variations in process characteristics and/or operating temperature that may occur within the surface of the integrated circuit chip. Thus, each plurality of one or more valves 104A-140H may be affected by operating temperature and/or process characteristics that are local to the physical region in which the valves 104A-104H are located. In one embodiment, the gates 104A-104H may be selected from the "spare gates" that are typically contained throughout the integrated circuit chip 10 to allow logic errors in the logic circuit 14 to be corrected by changing the interconnect layer of the integrated circuit chip. Thus, the spare gates are not initially connected to logic circuit 14 and are not used. If errors are detected in the logic, spare gates can be connected to logic circuit 14 to form the correct logic function. Many different logic gates can be included in the spare gates to increase the likelihood of generating the correct logic function. Accordingly, unused spare gates may be varied and may be connected together to create a daisy chain connection of gates 104A-104H that can be scaled similar to logic circuit 14. When implementing gates 104A-104H from spare gates, gates 104A-104H may not be added to the semiconductor section , used for integrated circuit 10.

In addition, using a series connection of logic gates 104A-104H for delay detection is primarily a digital circuit. Thus, in some embodiments, use of the circuit may be relatively simple and require little power compared to analog circuitry.

The measurement module 100 includes at least electrical circuitry configured to trigger a transition and measure a propagation delay. In some embodiments, measurement module 100 may also include circuitry configured to determine when to take a measurement and/or circuitry configured to compare the propagation delay to an expected value.

According to another embodiment, the determination may be performed in the local power management device 18 or in software.

Typically, a logic gate includes electrical circuitry that receives one or more input signals, and is configured to perform a logic function on the input signals to provide one or more output signals. One or more such gates may be included in each plurality of gates 104A-104H. It should be noted that although gates 104A-104H are shown near the boundary of logic circuit 14 in FIG. 6 for graphical convenience, gates may typically be interspersed throughout portions of logic circuit 14 as mentioned above.

Although the above discussion of FIG. 6 mentioned requesting a supply voltage value and the PMU/power supply 12 supplying a voltage of the requested value, the discussion did not imply that there is only one request/supply voltage. There may be multiple supply voltages that are requested and supplied at any given time. For example, there may be separate supply voltages for the combinatorial logic circuitry and for the memory circuitry in logic circuit 14. There may be multiple voltage regions within the integrated circuit 10 that can be turned on and off separately, and may have separate measurement modules and sequential logic circuits. valves. Each such area can contain a separate request. Local power management device 18 may be powered separately from logic circuit 14. Any set of one or more power supply voltages may be requested and supplied. Additionally, in some embodiments, more than one chain of gates may be implemented within a voltage region to model different types of delays. For example, logic gate delays and register file delays can be modeled separately.

Turning now to FIG. 7, a flowchart is shown that depicts one embodiment of testing the integrated circuit 10, as shown in FIG. 6, prior to mounting the integrated circuit into a package. The blocks shown in FIG. 7 may be performed on a test facility (eg, a wafer tester) during production of the integrated circuit 10.

Similar to the embodiment of FIG. 2, the test may begin with testing to approximate the characteristics of the integrated circuit 10 (block 30), such as Iddq testing, and a set of test voltages may be selected (block 32). The test instrument may set the first test frequency (block 34), and may perform a test sequence for each voltage in the set of test voltages as the supply voltage (block 36). In this embodiment, the test may comprise activating the measurement module 100. For each test voltage, the test apparatus may count the number of delay cycles "N" measured by measurement unit 100 during the test (ie, the value in flip-flop counter 108). The test instrument may record the measured N for each test voltage (block 110). The tester may then select the minimum supply voltage value for which the test passes, as well as the corresponding "N" (block 112).

If there are additional test frequencies (for example, additional supported operating frequencies for IC 10 that have not yet been tested - branch block 40, branch "yes"), then the next frequency (blocks 34, 36, 110 and 112) can be selected and tested ). The set of test voltages may contain different voltages that will be tested at each supported operating frequency, or it may be selected such that at least one supply voltage is expected to pass the test for each supported operating frequency. Once the test frequencies are exhausted (branch block 40, tap "no"), the test apparatus can record the frequencies, voltage values, and "N" values ​​in the F/V/N table 102 (block 114).

In some embodiments, an allowance may be added to the measured "N" which will be recorded in the table. According to another embodiment, the allowance may be added to the "N" read from the table to write "N" to the flip-flop 106. Likewise, the allowance may be added to the supply voltage value recorded in the table, or the allowance may be added locally power management device 18 after reading the value from the table.

Turning now to FIG. 8, a flowchart is shown that depicts the operation of one embodiment of the integrated circuit 10 as shown in FIG. 6 (and in particular the measurement module 100 and the local power management device 18) in determining whether the supply voltage value needs to be adjusted. . The operation of FIG. 8 may be performed periodically while the integrated circuit 10 is operating (eg, in one embodiment, depending on the thermal inertia of the system, approximately once every 10 microseconds to 1 milliseconds). The operation of FIG. 8 may be performed after the workload has changed (eg, from operating in telephone mode to operating in audio player or mobile Internet access device mode). Also, the operation of FIG. 8 may be performed as part of changing the operating frequency. The blocks are shown in a specific order for ease of understanding, but other sequences may be used. The blocks may be executed in parallel by combinatorial logic in the measurement module 100/local power management device 18. Blocks, combinations of blocks, and/or the flowchart as a whole can be executed in a pipeline manner over multiple clock cycles.

Local power management device 18 may activate measurement module 100, which may measure the current propagation delay (“N”) in the series connection of gates 104A-104H (block 120). In some embodiments, local power management device 18 and/or measurement module 100 may filter the results (block 122). Namely, the filtering may comprise, for example, detecting fluctuations in the value of N between successive measurements. Jitter can occur because the propagation delay is close to an integer number of clock cycles (and thus is sometimes fixed to M clock cycles and sometimes M+1 clock cycles). Fluctuation may also occur due to the requested supply voltage increasing and decreasing in an oscillatory manner.

If the measurement module 100 detects that the measured "N" is greater than the "N" from the F/V/N table 102 (branch block 124, tap "yes"), then the local power management device 18 may increase the requested supply voltage value sent to PMU/power supply 12 (block 126). For example, the next higher supply voltage value may be requested. If the measurement module 100 detects that the measured "N" is less than the "N" from the F/V/N table 102 (branch block 128, tap "yes"), then the local power management device 18 may reduce the requested supply voltage value sent to PMU/power supply 12 (block 130). The operation of FIG. 8 may be repeated until the requested supply voltage value is established, or may be repeated during the next measurement, as desired.

Turning now to FIG. 9, a flowchart is shown that depicts the operation of one embodiment of the integrated circuit 10 (and in particular the local power management device 18 and measurement module 100) in response to a frequency change request in the integrated circuit 10. Blocks are shown in a specific order for ease of understanding, but other arrangements may be used. The blocks may be executed in parallel by combinatorial logic in the measurement module 100/local power management device 18. Blocks, combinations of blocks, and/or the flowchart as a whole can be executed in a pipeline manner over multiple clock cycles.

If the frequency change request is a request to increase the current operating frequency (block 140, branch yes), the value of N in flip-flop 106 may be scaled according to the ratio of the new (requested) frequency to the old (current frequency) (block 142). For example, if the current frequency is 1 GHz and the new frequency is 1.5 GHz, then the N value can be scaled by 1.5. Local power management device 18 and measurement module 100 may repeat the supply voltage adjustment process of FIG. 8 until the measured N from measurement module 100 matches the scaled N (block 144). In some embodiments, an allowance may be added to the scaled N to ensure that the increased supply voltage is sufficient to support the newly changed frequency. Once the scaled N is reached, local power management device 18 may set the new frequency (block 146) and may wait for the clock circuit to lock at the new frequency (block 148). The new N may be read from F/V/N table 102 and may be written to flip-flop 106 (block 150).

If the frequency change request is a request to reduce the current operating frequency (branch block 140, tap no), local power management device 18 may set the new frequency (block 146) without scaling N and adjusting the supply voltage (blocks 142 and 144). Since the supply voltage is already high enough to support the higher current frequency, the integrated circuit 10 will operate at the new frequency without errors. Subsequent periodic measurements and adjustments (eg, Fig. 8) can lower the voltage. In other embodiments, N may be scaled and the voltage may be adjusted (blocks 142 and 144) also for the new lower frequency, in which case the supply voltage adjustments will be downgrades.

In some embodiments, the process of adjusting the supply voltage value (block 144) may begin by reading the supply voltage value from the F/V/N table 102 (or self-calibration table 22) for the new frequency and initiating the process when requesting the supply voltage value from the table.

Referring now to FIG. 10, a flowchart is shown that depicts another embodiment of testing the integrated circuit 10 as shown in FIG. 6 prior to mounting the integrated circuit into the package. The blocks shown in FIG. 10 may be performed on a test facility (eg, a wafer tester) during production of the integrated circuit 10.

Similar to the embodiment of FIG. 2, the test may begin with testing to approximate the characteristics of the integrated circuit 10 (block 30), such as Iddq testing. In addition, the measurement module 100 may be activated with the maximum possible supply voltage set value (according to the specification of the integrated circuit 10) (block 160). The measurement of N at its maximum possible value may be an indication of the "speed" of the integrated circuit 10 and may be used to select a set of test voltages (block 162). Thus, the selected test voltages may be closer to the optimal voltage for a given frequency, which may allow small step voltage testing in a small amount of test time and result in a supply voltage value close to the optimal value for the integrated circuit 10. Accordingly, the integrated circuit 10 may consume less power at a given frequency when the supply voltage is set equal to the table voltage (compared to less optimal testing strategies). In addition, a relatively small set of voltages can still be used, reducing testing time. For example, FIG. 13 is a graphical representation of the distribution of instances from the fast process (left side of FIG. 13) to the slow process (right side of FIG. 13). Using the maximum voltage (dashed line furthest to the right), N can be measured. Based on the measured N, a small set of test voltages around the expected operating point can be selected, and the integrated circuit 10 can be tested at these voltages (curly bracket at the bottom of Fig. 13) .

Subsequently, similar to the embodiment of FIG. 7, the first test frequency is set (block 34) and a test sequence can be performed for each voltage in the set of test voltages as the supply voltage (block 36). The test may include activating the measurement module 100. For each test voltage, the test instrument may read the number of delay cycles "N" measured by measurement module 100 during the test (ie, the value in counter flip-flop 108). The test instrument may record the measured N for each test voltage (block 110). The tester may then select the minimum supply voltage value for which the test passes, as well as the corresponding "N" (block 112).

If there are additional test frequencies (for example, additional supported operating frequencies for IC 10 that have not yet been tested - branch block 40, branch "yes"), then the next frequency (blocks 34, 36, 110, and 112). The set of test voltages may contain a different test voltage for each supported operating frequency, or may be selected such that there is at least one passing supply voltage for each supported operating frequency. Once the test frequencies have been exhausted (branch block 40, tap "no"), the test apparatus can record the frequencies, voltage values, and "N" values ​​in the F/V/N table 102 (block 114).

In some embodiments, an allowance may be added to the measured "N" that will be recorded in the table. According to another embodiment, the allowance may be added to the "N" read from the table to write the "N" to the flip-flop 106. Likewise, the allowance may be added to the supply voltage value recorded in the table, or the allowance may be added by the local device 18 power management after reading the value from the table.

Referring now to FIG. 11, a flowchart is shown that depicts the operation of one embodiment of measurement module 100 to perform a measurement. The measurement module 100 may perform the operation depicted in FIG. 11, for example, in response to a measurement being initiated by the local power management device 18. The blocks are shown in a specific order for ease of understanding, but other arrangements may be used. The blocks may be executed in parallel by combinatorial logic in the measurement module 100 . Blocks, combinations of blocks, and/or the flowchart as a whole can be executed in a pipeline manner over multiple clock cycles.

Measurement module 100 may clear the counter in flip-flop 108 (item number 170), and may initiate a logical transition in a series connection (or “chain”) of gates 104A-104H (block 172). If measurement module 100 has not yet detected a corresponding logic transition at the rung pin (branch block 174, branch no), then measurement module 100 may increment the counter (block 176) and wait for the next clock cycle to detect the transition again (block 178). If measurement module 100 detects a corresponding transition (branch block 174, branch "yes"), then measurement module 100 can compare the counter with N in flip-flop 106 and report the results to local power management device 18 (block 180).

Numerous variations and modifications will become apparent to those skilled in the art once the above disclosure is fully understood. The following claims are intended to be interpreted so as to cover all such variations and modifications.

1. An integrated circuit configured to generate a requested supply voltage value for the integrated circuit, wherein the integrated circuit comprises:
logic circuit;
a local power management device coupled to the logic circuit and configured to transmit an indication of the requested supply voltage value to an external power source; and a self-calibration module in the integrated circuit, which is configured to perform a logic circuit test, wherein the self-calibration module is configured to repeat the test at correspondingly lower requested supply voltage values ​​until the test fails, and wherein the lowest requested voltage value power supply at which the test passes is used to generate a requested supply voltage value for operation of the integrated circuit, and wherein the self-calibration module is further configured to repeat the test and determine the lowest requested supply voltage value in response to the logic circuit executing a different workload.

2. The integrated circuit of claim 1, further comprising a static table of supply voltage values, wherein the contents of the static table are determined during a factory test of the integrated circuit, and wherein the local power management device is configured to read the initial supply voltage value from the static table.

3. The integrated circuit of claim 1, wherein the integrated circuit is capable of operating at a plurality of clock frequencies, and wherein the self-calibration module is configured to repeat the test at correspondingly lower supply voltage values ​​for each of the plurality of clock frequencies to determine the lowest requested voltage value. power supply for each of the multiple clock frequencies.

4. The integrated circuit according to claim 1, wherein the self-calibration module is configured to repeat the test in response to booting up the device that includes the integrated circuit.

5. The integrated circuit of claim 4, wherein the self-calibration module is configured to repeat the test and determine the lowest requested supply voltage value in response to the age of the integrated circuit exceeding a certain value.

6. The integrated circuit according to claim 1, wherein the local power control device comprises a self-calibration table configured to maintain the lowest supply voltage values ​​determined by the self-calibration module, and wherein the local control device, in response to a request to change the operating frequency of the integrated circuit, is configured check the self-calibration table for the lowest supply voltage value corresponding to the operating frequency, and wherein the local control device, in response to detecting that the lowest supply voltage value corresponding to the operating frequency is not stored in the self-calibration table, is configured to call the self-calibration module to repeat test at correspondingly lower requested supply voltage values ​​until the test fails to determine the lowest supply voltage value for the operating frequency.

7. The integrated circuit according to claim 6, wherein the local power management device is configured to determine whether to invoke a self-calibration module in response to detecting that the lowest supply voltage value corresponding to the operating frequency is not stored in the self-calibration table, and wherein locally The control device is configured to request the value of the supply voltage determined during the factory test of the integrated circuit, in response to the determination not to call the self-calibration table.

8. A method for generating a supply voltage value for an integrated circuit, the method comprising the steps:
repeating the logic circuit test by the self-calibration module at correspondingly lower requested supply voltage values ​​for the integrated circuit that contains the logic circuit and the self-calibration module until the test fails;
determining, through the self-calibration module, the lowest requested supply voltage value at which the test is successful;
selecting, by the self-calibration module, the lowest requested supply voltage value to generate the requested supply voltage value for operating the integrated circuit, the method being performed in response to the logic circuit executing a different workload.

9. The method of claim 8, further comprising reading the initial requested supply voltage value from a static table, the contents of the static table being determined during a factory test of the integrated circuit.

10. The method of claim 8, wherein the integrated circuit may operate at a plurality of clock frequencies, and the method further comprises repeating the steps of repeating, determining, and selecting for each of the plurality of clock frequencies.

11. The method of claim 8, performed in response to booting up a device that includes an integrated circuit.

12. The method according to claim 11, performed in response to the age of the integrated circuit exceeding a certain value.

13. The method according to claim 8, further comprising the steps of:
in response to a request to change the operating frequency of the integrated circuit, checking a self-calibration table for the lowest supply voltage value corresponding to the operating frequency, wherein the self-calibration table is configured to maintain the lowest supply voltage values ​​determined by the self-calibration module; and in response to determining that the lowest supply voltage value corresponding to the operating frequency is not stored in the self-calibration table, causing the self-calibration module to repeat the test at correspondingly lower requested supply voltage values ​​until the test fails to determine the lowest supply voltage for the operating frequency.

The invention relates to methods for reducing power (energy consumption) in a processor. .

The invention relates to computing devices such as mobile phones and personal digital assistants (PDAs). The technical result is to reduce energy consumption and increase the battery life of the device by identifying plans based on the received notification of resource availability, activation time and tolerance factor. The method comprises: receiving an event notification, wherein the received event notification indicates that a resource associated with a computing device is available; accessing a plurality of repeating plans, each of said plurality of repeating plans having a predetermined activation time and a tolerance factor associated with it; identifying one or more plans being accessed as a function of the received event notification, the current time, a given activation time, and a tolerance factor of each of the plans being accessed; and activating the identified plans to consume said available resource. 3 n. and 17 salary f-ly, 4 ill., 6 tables.

The invention relates to means for providing energy-saving thread scheduling and dynamic use of processors. The technical result is to reduce electricity consumption. It is determined which cores from said plurality of cores are actively performing work. Create a kernel suspend mask using a bit value to represent the suspended or running state of the kernel. Define thread-processor affinity masks that represent one or more cores that are assigned to process the thread. Provide at least a portion of the performance and power saving plan for the cores by combining the inverted core suspend mask and thread-to-processor affinity masks using the AND operator to create a set of available processors. It calculates which cores are designated as suspended or running based, at least in part, on the set of available processors. At least one of the cores actively performing work is suspended based at least in part on a power policy indicating that at least one of the cores actively performing work is designated as a suspended core. 3 n. and 15 salary f-ly, 8 ill.

The invention relates to portable computing devices and, more particularly, to portable computing device docking stations. The technical result is to increase the efficiency of power distribution control between a portable computing device (PCD) and a PCD docking station. The method comprises the steps of: determining that the PCD is docked with a PCD docking station; switching power to the PCD from the PCD battery to the PCD docking station battery in response to determining that the PCD is docked with the PCD docking station; powering the PCD and the PCD docking station from the battery of the PCD docking station; determining whether the energy of the PCD battery is equal to the charging condition; charging the PCD battery from the PCD docking station battery when the energy of the PCD battery is equal to the charging condition; battery energy monitoring of the PCD docking station; determining whether the battery energy of the PCD docking station is equal to a critical condition; and switching the power supply to the PCD and the PCD docking station from the PCD docking station battery to the PCD battery when the energy of the PCD docking station battery is equal to the critical condition, and powering the PCD and the PCD docking station from the PCD battery. 4 n. and 28 salary f-ly, 34 ill.

The invention relates to a circuit of a household appliance. The technical result is to reduce energy consumption in standby mode of a household appliance. To this end, an electrical household appliance is provided comprising a low-voltage capacitive power supply connected to an electrical power supply network and designed to generate a low voltage, wherein the low-voltage capacitive power supply comprises a capacitive divider circuit comprising first and second input terminals connected to the first and second power lines , which are under the first and second given potentials, respectively; a first output terminal configured to generate said low-voltage turn-on signal, first and second charge storage means connected between said first and second input terminals; and at least one voltage limiter connected in parallel to said charge storage means and configured to switch from a non-conducting state to a conducting state when applied to a voltage that exceeds a predetermined breakdown voltage; wherein the first and second charge storage means are designed such that the voltage at the terminals of the second charge storage means is lower than said predetermined breakdown voltage. 14 salary f-ly, 5 ill.

The invention relates to the field of means for instructing a device to enter an active mode. The technical result is to reduce the energy consumption of the device. The system includes a first sensor (3) for determining whether a first condition related to the user's coarse level of interest (9) is satisfied; a second sensor (5) for determining whether a second condition relating to a more precise level of interest of the user (9) is satisfied in response to the first sensor (3) determining that the first condition is satisfied by measuring another parameter or by applying a more precise test to measure the same parameter; and a device (7) for entering an active mode in response to a determination by the second sensor (5) that the second condition is satisfied, the active mode being a mode for notifying the user that the device is turned on. The first sensor (3) is further configured to determine whether a third condition related to a third user interest level more precise than the first user interest level (9) is satisfied. The device (7) is further configured to transition from a mode of notifying the user that the device is turned on to a mode of interacting with the user in response to the determination by the first sensor (3) that the third condition is satisfied. 3 n. and 8 z.p., 7 ill.

The invention relates to a method for operating a processor in a real-time environment. The technical result is a reduction in energy consumption. In the method, after processing a real-time event, the processor switches from the operating state to the rest state. Upon the impending occurrence of a subsequent real-time event, an auxiliary signal is generated by which the processor switches to an operating state before the onset of a subsequent real-time event, whereby a rise or fall of a parameter below a predetermined auxiliary threshold value is detected by at least one auxiliary sensor, and by the auxiliary sensor an auxiliary signal is generated, and the auxiliary threshold value is reached during the change in the parameter value before the threshold value. 6 salary f-ly, 2 ill.

A group of inventions relates to remote control devices. The technical result is to increase the range of the remote control device in the system while minimizing the power consumption of the entire system. To this end, the invention describes a device control system, the system comprising a remote control module for transmitting a signal in the form of electromagnetic radiation and a repeater module comprising a detector for detecting electromagnetic radiation to obtain a repeater reception signal and a first signal conversion module for passively converting the repeater reception signal into a signal repeater switching drives for activating a first switch to switch the repeater module between an inactive mode in which the repeater module is completely disconnected from the first power source such that the repeater module does not consume any current, and an operating mode in which current is consumed by the repeater module from the first source nutrition. The repeater module further includes a signal module, powered by the first power supply, for generating a repeater transmission signal based on the repeater reception signal, and a repeater transmission interface for relaying the repeater transmission signal in the form of electromagnetic radiation. The system also includes a controllable device comprising a remote control interface module for detecting electromagnetic radiation transmitted by the repeater transmission interface to obtain a device reception signal. 3 n. and 11 salary f-ly, 12 ill.

The invention relates to a data processing device and a method for switching a workload between a first and a second arrangement of processing circuits, in particular to a method for increasing the processing performance of a workload after said switch. The technical result is to reduce the delay when switching the workload. In the apparatus, to reduce the number of memory accesses required by the target circuit layout after migration, the source circuit layout cache is maintained in a power-on state during the scan period. During the lookup period, the cache lookup circuit layout looks up the data values ​​in the source cache and retrieves the lookup data values ​​for the target lookup pattern layout. 3 n. and 28 salary f-ly, 19 ill.

The invention relates to the field of electrical engineering, and more specifically to methods for analyzing power consumption in complex computing and communication systems. The technical result is to increase the accuracy of energy consumption assessment. The method comprises the steps of: a) calibrating the device by: configuring and starting the device; disconnecting from an external power source; launching a test application; collecting and transmitting data to the main system; repeating all previous steps for each test application; calculating the necessary time data, calculating model coefficients using the method least squares; b) perform an assessment of energy consumption by: configuring and starting the device; launching the analyzed application; collecting data and transmitting data to the main system; calculating the necessary time data; calculating the charge consumed during the operation of the application, both separately for each factor and the total, as well as the relative contribution of user functions, using a linear model and coefficients found at the calibration stage. 8 ill.

The invention relates to computer technology, namely to image formation systems. The technical result is to increase the activation speed of the image forming device. An image forming device has been proposed. The apparatus includes a switching unit configured to switch the state of the imaging apparatus from a first state to a second state in a case where the power switch is turned off, and switch the state to a first state in a case when the power switch is turned on. Also, the device includes a retrieval unit configured to retrieve a turn-off time period during which the power switch was turned off in a case where the power switch is turned on. In addition, the device also includes a wake-up control unit configured to issue a system reset command and to restart the imaging apparatus in a case where the shutdown time period is not greater than a predetermined time period, and to return the imaging apparatus from the second state to the first state. state without issuing a system reset command in the case where the shutdown time period is longer than a predetermined time period. 6 n. and 13 salary f-ly, 6 ill.

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1 INTELLIGENT ELECTRIC POWER SYSTEM WITH AN ACTIVE-ADAPTIVE NETWORK: STRUCTURE, METHODOLOGICAL PRINCIPLES, CONTROL SYSTEM Irkutsk, 2013

2 Outline of the report 1. Introduction 2. Prospective directions for the development of UES of Russia 3. Principles of formation of IES AAS 4. Hierarchical adaptive control of IES AAS modes 5. Information support for control of IES AAS 6. Subsystems of automatic, operational and emergency control of IES AAS 7. Prospects for application of the results work and further development of the ideology of IES AAS 8. Conclusion

3 Introduction The UES of Russia, created more than 60 years ago, is a unique organizational and technical facility. However, the centralized system of organization and management of the UES in the conditions of modern post-reform Russia needs radical modernization. In recent decades, we have to talk about the unsatisfactory state of the technological potential of the Russian electric power industry. To solve existing problems, it is necessary to transition the domestic electric power industry to a new quality of management through the formation of an integral multi-level management system with an increase in the volume of automation and an increase in the reliability of the entire system, including the weakest and most vulnerable links.

4 In the last decade, Smart Grid technology (smart network) has been developing in advanced countries of the world. There are already dozens of pilot projects where the use of “smart meters”, “smart elevators”, “smart houses”, the use of solar and wind energy in combination with “smart houses” gives a significant benefit to the consumer in paying for services energy organizations. Introduction Electricity supply organizations receive a positive effect due to smoothing the peak load schedule and reducing electricity losses.

5 Introduction By analogy with the Smart Grid concept, the transition of the Russian electric power industry to an intelligent level involves the creation of a new technological platform of the UES of Russia, an intelligent energy system with an active adaptive network (IES AAS). In 2010, the concept of IES AAS was developed by JSC Scientific and Technical Center of Electric Power Industry and approved by JSC FGC UES. IES AAS represents a customer-oriented EPS of a new generation, which should ensure availability of resource use, reliable, high-quality and efficient service to electricity consumers through flexible interaction of all its subjects (all types of generation, electrical networks and consumers) based on modern technological means and a unified intellectual hierarchical control systems.

6 Transition to an intelligent energy system with an actively adaptive network Main functions of the UES of Russia Generation Transmission and distribution of electricity Consumption Existing UES of Russia Priority of large-scale generation (active control based on assignment) Passive transmission system (control of generation, consumption, control due to switching) Free use of electricity by the consumer, taking into account external restrictions of IES AAS Transition to a qualitatively new smart energy system Any generation, incl. non-traditional and distributed. Active control with overall coordination of IES AAS Active-adaptive transmission system with real-time control Figure. 1. Flexible, efficient use of electricity, adapting to the system situation

7 Technological infrastructure of IES AAS Renewable and non-renewable energy sources Renewable and non-renewable energy sources Parameter control systems: - power flows - voltage - frequency, etc. Traditional generation Unified national electric grid Distributed networks Active consumers Intelligent power supply systems Intelligent power supply systems Adaptive consumption control system Devices measuring: - electrical load - voltage modules - voltage phase - network resistance Energy storage devices Preventive monitoring and control systems Adaptive control system Intelligent energy system (Smart Grid) ) The main features of Smart Grid: - developed metering and measurement systems - adaptive consumption control system (ACS) - self-regulation systems of local sources (including non-renewable and renewable energy sources) - coordination from a common control system Figure. 2.

8 Definition of IES AAS IES AAS is a customer-oriented EPS of a new generation, which should ensure availability of resource use, reliable, high-quality and efficient service to electricity consumers through flexible interaction of all its subjects (all types of generation, electrical networks and consumers) based on modern technological means and a unified intelligent hierarchical management system. Customer-oriented IES AAS is a new level of relations between energy companies and electricity consumers with the formalization of relations in terms of reliability and quality of power supply.

9 New properties of the power system within the framework of the IES AAS concept To implement the IES AAS concept, it is necessary to provide the power system with new properties, including: interaction of the network with any type of generation, including small and alternative energy sources; network interaction with consumers based on effective use electricity due to situational load regulation with maximum consideration of consumer requirements; creation of a new network topology of the electric power industry with hierarchical territorial and technological segmentation and flexible active-adaptive intersegment connections, ensuring exchanges and regulation of base, half-peak and peak powers using an appropriate automatic control system;

10 New properties of the power system within the framework of the IES AAS concept, the implementation of an adaptive response of the power system and electrical network to the current situation based on a combination of centralized and local control in normal and emergency modes; mastering new information resources and technologies to assess situations, develop and make operational and long-term decisions for implementation effective management; ensuring the expansion of market opportunities for infrastructure through the mutual provision of a wide range of services by market entities and infrastructure.

11 Generation in IES AAS

12 Network components of IES AAS

13 The concept of an active consumer The concept of IES AAS is aimed at implementing an active consumer strategy, which means ensuring that consumers can independently change the volume and functional properties of the electricity received based on the balance of their needs and the capabilities of the power system. In other words, it encourages consumers to participate in load management. In an intelligent power supply system, the end consumer of electricity is considered as a partner of power industry entities in terms of ensuring reliable operation of the power system and acquires the status of “active”.

14 The concept of an active consumer “An active consumer” has the right to choose: the mode of his electricity consumption in accordance with the need to fulfill production plans for production or provide energy to the household, optimizing the costs of purchasing electricity from external markets; the degree of their participation in the provision additional services controlled active and reactive loads (powers) for control by the System Operator; conditions for loading with own capacity (if available) for generating an application for participation in the purchase/sale of electricity on the wholesale and retail markets.

15 Basic subjects of the IES AAS Basic subjects Consumers Markets Service providers Operation and development Wholesale generation Transmission Distribution Subject objects End users of electricity: industry, transport, construction, business and commercial sector, households Market participants and Operators Organizations providing services to wholesale and retail entities markets Generating companies, electric grid organizations Generating companies Electric grid organizations Electric grid organizations and consumers of electricity Factors to be taken into account Ability to manage the use of electric energy, including the possibility of its generation and storage Ability to organize trade in electricity Availability of structures and technologies that ensure the provision of services Ability to provide management of operation and development power systems Table 1 Possibility of generating electricity, including its storage for further distribution Transmission of large quantities of electricity over long distances, including, if necessary, storage and generation of electricity Distribution of electricity to and from consumers, including, if necessary, storage and electricity generation

16 Hierarchical adaptive control of IES AAS modes: Functional control structure Control centers of IES AAS Operational dispatch control centers Software systems that form the control environment Application software systems (off-line, on-line) Software tools Centers for operational technological control Systems for issuing control actions Collection systems, processing and transmission of information Centers for collecting and processing data information Systems for exercising control actions Primary measurement systems Commercial metering systems Technical metering systems management Power facilities AAS (“digital substation”) Figure 3

17 Control levels of IES AAS Standard interface 1st level Standard interface AS dispatch control AS technological control AS control technological processes Mode management Quality control, electricity metering Measurements, control, diagnostics Hierarchical supervisory control system GENERATION (power, thermal and other installations) Instruments and equipment of electrical installations NETWORKS (transmission and distribution, substations, distribution points) Instruments and equipment of networks and substations 2nd level CONSUMERS (installations and networks) Level 3 Devices and equipment of consumers Figure 4

18 Hierarchy of levels (“quality”) of control in the IES AAS 6. Intelligent control a control system with built-in artificial intelligence functions that perform goal-setting functions. 5. Intelligent control - a control system with built-in artificial intelligence functions without a goal-setting function. 4. Adaptive control of changing the parameters of the controller or the structure of the controller depending on changes in the parameters of the control object or external disturbances acting on the control object. ENVIRONMENT 3. Robust control stable control under existing changes in the parameters of the control object or external disturbances acting on the control object 2. Positional control control of the specified state of the control object 1. Program control control of the specified trajectory of the object Control object Figure 5

19 Structure of hierarchical coordinated adaptive control of IES AAS modes UNIFIED CONTROL CENTER Situation center of the UES of Russia Hierarchical distributed information technology structure of dispatch and control centers of the energy sector 1st level dispatch centers of the System Operator (CDU, ODU, RDU), FGC UES (TsUS UNEG, territorial NCC) 2nd level IDGC control centers (TsUS RSK, TsUS PES) 3rd level Automated process control systems of FGC UES substations, Automatic process control systems of power plants, control centers of distribution networks Information and transport network based on the Unified Digital Communications Network of Electric Power Industry (UDCSE) Hierarchical complex of electrical equipment of devices and executives devices Operational and technological control points for consumers Figure 6

20 Requirements for the control system of the IES AAS 1. Increasing the degree of control automation in combination with effective advice systems for decision-making by operating personnel. 2. Coordination of the balance of interests of power industry entities and electricity consumers, subject to minimization of costs for energy supply and services. 3. Maximum use of the capabilities of the technological base of the energy sector while minimizing various types of restrictions. 4. Involving consumers in managing the energy system in emergency situations, taking into account their economic interests.

21 Requirements for the control system of the IES AAS 5. The maximum possible speed of decision-making on changing the conditions for using electricity, primarily in off-design situations. 6. Real-time monitoring of system stability, dynamic forecasting and preventive response to changing conditions external environment. 7. Possibility of reconfiguring parts of the system in emergency situations with restoration of normal operation. Protection of control systems and information space from targeted electromagnetic influences and cyber attacks.

22 Intelligent control technologies in IES AAS 1. Multi-agent control systems - coordination of control systems using a transient monitoring system (SMRS) and FACTS devices, self-healing of district EPS, demand management for local trading platforms. 2. Artificial neural networks (ANN) and neural network control systems, associative search for identification and control, expert systems for early detection and localization of pre-emergency modes, virtual modeling and model reduction, operator advisors, simulators). 3. Technologies of adaptive vector control of flexible alternating current systems - primary and secondary automatic control of voltage and reactive power, additional optimization of reactive power modes within the boundaries of the load schedule established by the CO. 4. Adaptive real-time modeling platforms - modeling and optimization of reactive power modes, network topology monitoring and model adaptation, testing grounds for control and monitoring systems.

23 Intelligent control technologies in IES AAS 5. Technologies for designing, creating and maintaining large-scale information transmission systems in IES AAS system analysis, verification and validation of the system, modeling and monitoring of information network parameters for timely identification of problem areas in information structure IES AAS. 6. Adaptive automatic control technologies for renewable energy sources (RES), including wind, tidal, solar, incl. in the future of space solar power plants. 7. Technologies for creating modern human-machine interfaces based on the use of personal mobile intelligent information input-output devices (wearable and mobile computers, smartphones), to ensure flexible control in a distributed resource-user structure.

24 Information support for IES control AAS: Time diagram of monitoring, forecasting and control Point in time for assessing the state Current point in time Point in time for monitoring the state Point in time for automatic control signals Point in time for dispatch control control t Interval for data collection Interval for assessing the state and forecasting Interval for implementation of automatic control signals Figure 7 Interval for implementation of dispatch control control signals

25 Tasks of the monitoring, forecasting and control block in the IES AAS The monitoring and forecasting blocks of normal, pre-emergency and post-emergency modes of the EPS for control purposes include the following tasks: assessment of the state (OS) of the system; forecasting the parameters of the upcoming mode - the OS gives only a current assessment of the mode with a certain delay, but for the tasks of monitoring and controlling the IES AAS, some anticipation of the assessment of the system state is required (“to manage means to anticipate”); assessment of weaknesses in the system in the upcoming regime; grade throughput connections in the upcoming mode - necessary for the effective use of reserves during operational and automatic control due to appropriate control actions; visualization of the upcoming regime; determination of indicators and criteria for transition from normal to pre-emergency mode and back, as well as from post-emergency mode to normal.

26 State assessment problem in IES AAS In ISEM SB RAS, the main directions for the development of state assessment (OS) methods were formulated to obtain the most complete picture of the current state of IES AAS: 1. Decomposition of the OS problem when calculating smart power systems with a multi-level hierarchical structure based on modern network technologies and multi-agent approaches. 2. Use of synchronized measurements of complex electrical quantities (PMU data) to improve the efficiency of EPS OS algorithms and OS problem decomposition algorithms. 3. Increasing the efficiency of teleinformation authentication algorithms (TI and TS). Development of methods for checking the reliability of PMU measurements based on a priori methods for TI verification. 4. Use of robust OS criteria; 5. Application of artificial intelligence methods (neural network and multi-agent technologies, genetic algorithms, simulated annealing) in OS algorithms 6. Use of dynamic algorithms to validate measurement information, calculate the current mode (state assessment) and predict the modes of IES AAS.

27 Intelligent forecasting in IES AAS Significant changes in global and Russian energy recent years, such as: the complication of the topology of power systems, the increase in the share of renewable energy sources, the development of a competitive electricity market, lead to the fact that changes in the main parameters of the regime and various characteristics of the EPS become unpredictable, sharply variable, which forces engineers and researchers to turn to new, more complex forecasting models. In such conditions, traditional statistical and regression approaches do not allow achieving the necessary forecast accuracy, which is extremely important in modern electric power calculations. Therefore, developments in recent years have been focused on the development of predictive approaches based on algorithms and artificial intelligence methods: neural network technologies, expert systems, machine learning models, fuzzy computing, the ideology of “data mining”, committee methods

28 Intelligent forecasting in IES AAS Despite the advantages of intelligent forecasting algorithms noted in a number of articles in recent years, many researchers believe that the question of high efficiency, for example, neural networks (ANN) or fuzzy systems, in solving the forecasting problem still remains open. An intelligent solution to the cases noted above seems to be the use of hybrid approaches and models, when combining various intelligent and traditional models allows us to obtain the most effective solutions, primarily guaranteed forecast accuracy. Promising hybrid models at this stage include the following combinations: ARI and ANN, fuzzy systems and ANN, expert systems and ANN, Hilbert-Hung transforms with ANN and support vector machine models, etc.

29 Hybrid model of PGC+INS+MOV for short-term forecasting Initial data (from the SCADA system, PMU sensors. Telemetry) Parameters of the EPS mode Hilbert-Huang transform Decomposition into empirical modes Guang transform Modes, frequencies, amplitudes Feature extraction and data selection Genetic algorithms Boosting decision trees Random Forest algorithm Ready training sample Selection of the optimal forecast model Artificial neural networks Support vector machines Test sample Testing forecast models Fig. 8 General diagram of the hybrid approach for creating predictive models Fig. 9. Decomposition of the original implementation into empirical modes (transformation of the time series forecasting problem into a regression problem)

30 Average forecast error, MAPE, % Average forecast error, MAPE, % Application of the hybrid model PGH-INS-MOV for short-term forecast of power flow and electricity prices active power flow, MVt real active power flow HHT-GA-ANN model forecast HHT- GA-SVM forecast time (minute) Expon. smoothing ARISS ANN Hybrid PGC-MOV Fig. 10. Results of forecasting power flow “1 minute ahead” Hybrid UGH-INS 7 6 actual wind speed forecast based on a hybrid model Wind speed Time (hours) ANN Hybrid UGH-MOV Fig. 11. Results of forecasting wind speed for “24 hours ahead” Hybrid UGH-INS

31 Intelligent monitoring of operating modes of IES AAS The concept of intelligent monitoring includes the following actions: data collection - this data is fed into a data preliminary processing system, which determines the most important and critical data that influences the development of the mode. classification (clustering) of EPS states - the purpose of this procedure is to determine how dangerous a particular state of the system is. interpretation of the resulting clusters (states) of the state so that the operator can develop preventive measures

32 Intelligent system for monitoring and assessing the safety of EPS operating modes for early detection of emergency conditions The main idea of ​​using the Kohonen neural network classifier is to create a model that learns to classify various states of EPS, identify and predict emergency situations (Fig. 12) to warn the operator and launch a preventive system management. The autonomous process generates a cluster model for assessing the safety of the EPS state for direct online use. The cluster system is trained on the basis of a set of training examples that randomly generate random situations in the EES. IN online mode, real-time measurements are used, which are fed into the trained model from the SCADA system. Online mode 1. Formation of a sample Collection of data from sensors Data preprocessing (normalization) Electric power network SCADA 1. Sampling of measurements Data selection Data preprocessing 2. Clustering scheme 2. Safety assessment Clustering model for safety assessment Security state probability of a forecast state in % Off- online mode Fig. 12. Basic block diagram of the proposed approach for assessing and classifying the state of the system

33 Examples of intelligent models and systems for IES AAS Table 2 Intelligent models and systems Software intelligent agents and multi-agent systems in network information and control systems Intelligent fuzzy systems with virtual associative search models Control systems with distributed predictive models Neural network intelligent systems for recognizing emergency conditions and predicting the future mode Training expert systems Expert systems dispatcher assistants Purpose Automatic solution of a set of problems for managing normal, situational, and emergency modes of power plants, electrical networks, control systems Detection and localization of pre-emergency modes, assessment of the dynamics of participation of generating facilities of the global energy system Management of normal, situational, and emergency modes of power plants , electrical networks, control systems Detection and localization of pre-emergency modes, forecasting parameters of the upcoming operating mode Training of operator-dispatchers to control EPS in situational modes Monitoring the degree of static stability of EPS

34 Operational and dispatch control of IES AAS modes New means of measuring power system mode parameters (PMU, digital measuring devices) and controlling them (FACTS, energy storage devices, etc.), radically increasing the observability and controllability of power systems, modern means communications, new information technologies and artificial intelligence methods, highly efficient computer tools that fundamentally change the processes of collecting, processing, transmitting, presenting (visualizing) and using information, make it possible on a new basis to significantly increase the efficiency of operational dispatch control of IES AAS modes. The development of operational dispatch control methods is associated with the improvement of information support, automation of the preparation of operational decision options, automation of control, increasing the share of automatic control in the tasks of regulating and limiting mode parameters, automation of calculations of optimal modes and their implementation, etc. while maintaining control from the operational dispatcher personnel in the required amount.

35 Monitoring systems for limit modes within the AAS IES The block diagram (Fig. 13) shows the place of the ANN, which is used to prepare calculation information, and the place of the limit mode OS in the process of controlling the AAS IES. Using SCADA and WAMS, information about the EPS is collected. The received data after the certification block is sent to the input of the ANN. The response of the trained ANN is the values ​​of the PI weighting coefficients for a given mode. These values ​​supplement the calculated data. Next, the limit mode OS is executed, and the results are sent to the EPS control point. On-line information Reliability Mode recognition using ANN OS of the maximum permissible mode of the IES AAS ANN response: values ​​of the weighting coefficients PI Calculation information of the EPS Figure 13

36 Emergency control in IES AAS: Echelons of the emergency control system Figure 14

37 Structure of the emergency control system Figure 15 shows the structure of the emergency control system, which consists of the following main blocks: telemetry system, knowledge base, block for calculating control actions of the steady-state calculation module. The updated knowledge base contains information on the influence coefficients of loads and FACTS devices during various dangerous emergency outages, parameters of the FACTS regulatory characteristics, values ​​of damage caused to consumers by emergency outages, limits of transmitted power along power lines, technical and other restrictions, etc. Figure 15

38 Multi-agent emergency control system of IES AAS A promising approach in emergency control of IES AAS is the development of multi-agent emergency control systems (MAS PAC), which provide the ability to implement hierarchical intelligent control. Such a system is based on a decentralized structure, which ensures fast and reliable responses in both normal and emergency conditions. A multi-agent system itself is a distributed network of connected, self-regulating hardware agents that work together to achieve some common goal. In this approach, it is assumed that all serial devices of the power system such as: generators, power lines, transformers and power flow controllers are equipped with agents. An agent is defined as the hardware or software operating an entity in a virtual or real environment. Agents can work in competitive or cooperative modes depending on the state of the security system. Both types of agents have two goals: local - to maintain local parameters of the mode and operating characteristics of local equipment within acceptable limits, and global - to prevent a major accident. Agents within the MAS PAH coordinate their work by exchanging messages with each other.

39 Project of an intelligent system for preventing and eliminating emergency conditions based on multi-agent automation and Kohonen cards To control multi-agent automation, it is necessary to monitor and identify pre-emergency states of the EPS. For this purpose, the Kohonen network is used, which is trained offline and subsequently used online for monitoring, signaling and transferring MAS PAH agents to cooperation mode. SCADA data Security assessment system based on the Kohonen network (launching system) EPS status messages SCADA Multi-agent automation System A EPS mode parameters Advisor (top-level agent) System N System B Middle-level agent A Middle-level agent B... Middle-level agent N Agent of the lowest level A1 Agent of the lowest level A2 Agent Agent Agent Agent Agent Agent... lower lower lower... lower lower lower... level level level level level level Ak B2 B3 Bk N1 N2 Low level agent Nk System C Control actions Controllers influences Control actions Control actions Figure 16

40 Analysis of system reliability using the intelligent system MAS PAH + Kohonen and using conventional emergency automation U U401 U U402 U U403 U209 U U206 U U210 U U207 U407 Load Primary and Secondary Voltages, p.u Fig. 17 Changes in bus voltage without using an intelligent system U205 U401 U204 U402 U208 U403 U209 U404 U206 U405 U210 U406 U207 U407 Load Primary and Secondary Voltages, p.u Fig. 18 Changes in bus voltage using an intelligent system The lack of coordination between local PA devices caused a voltage avalanche, which led to the complete extinguishing of the subsystem in question with subsequent development of a cascade accident to nearby areas. After the implementation of the shock from the MAS PAH, the subsystem was able to maintain stability only through the coordination of reactive power sources. This did not require load shedding.

41 Project of a neural network system for emergency control of modes in the IES AAS In Fig. Figure 19 shows the structure of the PAH system, which consists of two ANNs. The first ANN is used to assess possible overloads caused by emergency shutdowns of electrical network elements. ANN training is carried out offline using a series of calculations of EPS modes for various circuit-mode situations. The second ANN serves to adapt the influence coefficients. Information on the post-emergency mode is supplied to the ANN input Figure 19

42 Automatic control in normal modes in IES AAS: “Immune” intelligent system of IES AAS In Fig. 20 shows two options for the architecture of the global “immune” system in the IES AAS. The main goal of the created system is early detection of the threat of instability in the power system and timely issuance of recommendations to the dispatcher for preventive control of modes in order to restore normal operation. In the first option (on the left), the specified model is restored by processing SMPR data on the state of the EPS, that is, by identifying the model parameters. In the second option (on the right), the model is “constructed” in real time in a real-time digital modeling platform based on processing TI and TS arrays. Figure 14

43 Further development and improvement of control tasks of IES AAS 1. Development of tasks of operational control of IES AAS based on new regulation of frequency and power flows (multi-agent systems, FACTS, PFC, etc.) 2. Development of intelligent algorithms and models for operational control systems of IES AAS (intelligent data analysis, Data Mining, committee analysis methods, neural network and multi-agent technologies, etc.) 3. Development and improvement of emergency control of IES AAS based on new software approaches (expert systems, neural network and multi-agent control systems) and new hardware means (FACTS, WAMS, PMU, ETC.) 4. Development of an automatic control system for IES AAS modes, creation of new information complexes, systems for intelligent monitoring of transient processes, “immune” systems for early detection of loss of stability, etc.

44 Conclusion - What has been done to create a new energy system in Russia? JSC FGC UES initiated and sponsored work on the creation of the AAS IES, including: The Concept for the creation of the AAS IES was developed and agreed upon with the System Operator. Developed general requirements to IES AAS. R&D has been and is being carried out to determine the basic technologies and systems aimed at creating elements of the IES AAS. Technical requirements for the creation of a test site for the software and hardware complex of the IES AAS have been developed. As part of the Scientific and Technical Center of FGC UES, the Center for System Research and Development of IES AAS was created to manage the implementation of a pilot project for the Eastern energy system.

45 THANK YOU FOR YOUR ATTENTION!

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We bring to your attention a complete description of the driver control panel. Please note that some settings are only available with certain types of equipment used. In this review, we tried to reflect all possible settings.

Main panel window

The main window is shown in the illustration:

The navigation panel is located on the left and allows you to navigate through the desired settings with one click. The View menu allows you to enable an advanced view, which gives you the most complete access to all driver settings options, or configure a custom panel view, leaving only those items that you intend to use. Also, in the lower left part of the panel, access to the control panel help system is provided (link “System Information”):

from which you can find out about the versions of files, installed drivers and other NVIDIA software, as well as the characteristics of the video card.

Category "3D Settings"

Adjusting images with playback

The following settings are available:

• Settings according to 3D application— this option allows you to control the quality and speed of display using 3D applications. However, the default trilinear filtering optimization and anisotropy sampling optimization enabled by default remain regardless of application settings.
• Advanced 3D image settings— advanced driver settings installed by the users themselves are used. The “Go” link provides access to the “Manage 3D Settings” tab. It is the management of additional driver options that allows you to achieve maximum image quality.
• Custom installations with a focus on...: - the most interesting option that allows simplified management of additional driver options for novice users:

Meaning Performance corresponds maximum speed work and includes settings: vertical synchronization is disabled, all optimizations (trilinear filtering optimization, mip filter optimization for anisotropy, sampling optimization for anisotropy) are enabled, negative level of detail: negative level prohibition - enabled, texture filtering - “quality”, control Anisotropic filtering and anti-aliasing are carried out by applications.

Meaning Balance has the following settings: anti-aliasing - 2x, anisotropic filtering - 4x, all optimizations (trilinear filtering optimization, mip filter optimization for anisotropy, sampling optimization for anisotropy) are enabled, negative level of detail - enabled, texture filtering - "quality", vertical sync - controlled by applications.

Meaning Quality has the following settings: trilinear filtering optimization - enabled, anti-aliasing - 4x, anisotropic filtering - 8x, negative level of detail - enabled, texture filtering - "quality", vertical synchronization - controlled by applications.

All modes are provided with detailed explanations of their use, and a rotating company logo demonstrates the use of certain settings.

For more detailed settings, use the window Managing 3D Settings.

Managing 3D Settings

Global options

Possible bookmark settings Global options :

Anisotropic filtering. Possible values ​​are “Off”, “Application control”, “2x-16x” (depending on the video adapter model). Anisotropic filtering is today the most advanced technique for compensating pixel distortion, and in combination with trilinear filtering it gives best quality filtration. Activating any value other than “Application Control” allows you to ignore application settings. But we should not forget that this is a very resource-intensive setting that significantly reduces performance.

Vertical sync pulse. Possible values ​​are “On.” and Off, Use 3D Application Setting. Vertical synchronization (it is completely unclear why NVIDIA moved away from this term) refers to the synchronization of image output with the monitor’s scan frequency. Enabling vertical synchronization allows you to achieve the smoothest possible image of the picture on the screen, turning it off allows you to get the maximum number of frames per second, often leading to disruption (displacement) of the image due to the fact that the video adapter has begun drawing the next frame, while the output of the previous one has not yet been completed . Due to the use of double buffering, enabling Vsync may cause frames per second to drop below the monitor's refresh rate in some applications.

Enable scalable textures. Possible values ​​are “None” and “Bilinear”, “Trilinear”. No - do not enable scalable textures in applications that do not support them. Bilinear - better performance at the expense of quality. Trilinear - good image quality with lower performance. It is highly not recommended to use this option in the forced bilinear filtering mode, since the image quality obtained when forcing the option is simply depressing.

Background lighting shading. Enabling technology for simulating global illumination (shading) Ambient Occlusion. The traditional lighting model in 3D graphics calculates the appearance of a surface solely based on its characteristics and the characteristics of the light sources. Objects in the light's path cast shadows, but they do not affect the illumination of other objects in the scene. The global illumination model increases the realism of an image by calculating the intensity of light reaching a surface, with the brightness value of each surface point depending on the relative position of other objects in the scene. Unfortunately, honest volumetric calculations of shading caused by objects in the path of light rays are still beyond the capabilities of modern hardware. Therefore, ambient occlusion technology was developed, which allows using shaders to calculate the mutual occlusion of objects in the plane of the “virtual camera” while maintaining acceptable performance, first used in the game Crysis. This option allows you to use this technology to display games that do not have built-in support for ambient occlusion. Each game requires a separate adaptation of the algorithm, so the option itself is enabled in the driver profiles, and the panel option only allows the use of the technology as a whole. The list of supported games can be found on the website NVIDIA. Supported on G80 (GeForce 8X00) and later GPUs starting with driver 185.81 in Windows Vista and Windows 7. May reduce performance by 20-50%. Possible values ​​are “On.” and "Off."

Maximum number of pre-prepared frames— allows you to limit the control of the maximum number of frames prepared by the central processor when disabled. If you encounter problems with a slow response of the mouse or joystick, you need to reduce the default value (3). Increasing the value can help achieve smoother images at low frame rates.

Expansion limitation. Possible values ​​are “Enabled” and “Disabled”. Used to solve compatibility problems with older OpenGL applications due to the overflow of the memory allocated for storing information about the capabilities of the video card. If applications crash, try enabling extension restriction.

Streaming optimization— allows you to control the number of GPUs used by applications; in most cases, changing the default value (Auto) does not require. However, some older games may not work correctly in such configurations. Therefore, it is possible to manage this option.

Power management mode. Possible values ​​are “Adaptive” (default) and “Maximum performance”. With GeForce 9X00 and newer video cards that have separate performance modes, for games and programs that place a small load on the GPU, the driver does not switch the video card to 3D performance mode. This behavior can be changed by selecting the “Maximum Performance” mode, then whenever the 3D graphics card is used, it will switch to 3D mode. These features are only available when using driver 190.38 or higher in Windows Vista and Windows 7.

Smoothing - gamma correction. Possible values: "On" and "Off." Allows you to perform gamma correction of pixels during anti-aliasing. Available on video adapters based on the G70 (GeForce 7X00) graphics processor and newer. Improves the color gamut of applications.

Anti-aliasing - transparency. Possible values ​​are Off, Multisampling, Oversampling. Controls advanced anti-aliasing technology to reduce the laddering effect on the edges of transparent textures. We draw your attention to the fact that the phrase “Multiple sampling” hides the more familiar term “Multisampling”, and the term “Redundant sampling” means “Supersampling”. The last method has the most serious impact on video adapter performance. The option works on video cards of the GeForce 6x00 family and newer, when using drivers version 91.45 and higher.

Antialiasing - parameters. The item is active only if the “Smoothing - Mode” item is set to “Increase application settings” or “Override application settings”. Possible values ​​are “Application control” (which is equivalent to the “Application control” value in the “Anti-aliasing - mode” item), and from 2x to 16x, including “proprietary” Q/S modes (depending on the capabilities of the video card). This setting has a serious impact on performance. For weak cards, it is recommended to use minimal modes. It should be noted that for the "Increase Application Settings" mode, only the 8x, 16x and 16xQ options will have an effect.

Antialiasing - mode. Enable full screen image anti-aliasing (FSAA). Anti-aliasing is used to minimize the "jaggies" effect that occurs at the boundaries of 3D objects. Possible values:

• “Application control” (default value) - anti-aliasing works only if the application/game directly requests it;
• “No”—completely disable the use of full-screen anti-aliasing;
• “Override application settings” - force the anti-aliasing specified in the “Anti-aliasing - parameters” item to be applied to the image, regardless of the use or non-use of anti-aliasing by the application. "App Settings Override" will have no effect on games using the technology Deferred shading, and DirectX 10 and higher applications. It may also cause image distortion in some games;
• "Increase Application Settings" (available only for GeForce 8X00 and newer video cards) - allows you to improve the anti-aliasing requested by applications in problem areas at a lower performance cost than using "Override Application Settings".

Error messages. Determines whether applications can check for rendering errors. The default value is “Off”, because Many OpenGL applications perform this check quite frequently, which reduces overall performance.

Appropriate texture binding. Possible values ​​are “Off.” , "Hardware is used", "OpenGL specification is used". By “texture snapping” we mean snapping texture coordinates beyond its boundaries. They can be snapped to the edges of the image or inside it. You can disable snapping if texture defects occur in some applications. In most cases, changing this option is not necessary.

Triple buffering. Possible values ​​are “On.” and "Off." Enabling triple buffering improves performance when using Vsync. However, you should remember that not all applications allow you to force triple buffering, and the load on video memory increases. Only works for OpenGL applications.

Accelerate multiple displays. Possible values ​​are Single Display Performance Mode, Multi-Display Performance Mode, and Compatibility Mode. The setting defines additional OpenGL parameters when using multiple video cards and multiple displays. The control panel assigns the default setting. If you have problems with OpenGL applications running on multiple graphics cards and displays, try changing the setting to compatibility mode.

Texture filtering - anisotropic filtering optimization. Possible values ​​are “On.” and "Off." When enabled, the driver forces the use of the point mip filter at all stages except the main one. Enabling this option slightly degrades the picture quality and slightly increases performance.

Texture filtering. Possible values ​​are " High quality", "Quality", "Performance", "High Performance". Allows you to control Intellisample technology. This parameter has a significant impact on image quality and speed:

• "High Performance" - Offers the highest possible frame rate, resulting in better performance.
• "Performance" - Setting up optimal application performance with good image quality. Gives optimal performance and good image quality.
• "Quality » is the standard setting that gives optimal image quality.
• "High quality" - gives the best image quality. Used to obtain images without using software optimizations for texture filtering.

Texture filtering - onegative deviation of LOD (level of detail). Possible values ​​are “Allow” and “Binding”. For more contrast-rich texture filtering, applications sometimes use a negative Level of Detail (LOD) value. This increases the contrast of a still image, but creates a “noise” effect on moving objects. To obtain a better image when using anisotropic filtering, it is advisable to set the option to “snap” to prohibit negative deviation of the LOD.

Texture filtering - trilinear optimization. Possible values ​​are “On.” and "Off." Enabling this option allows the driver to reduce the quality of trilinear filtering to improve performance, depending on the selected Intellisample mode.

Software settings

The bookmark has two fields:

Select a program to configure.

In this field you can see possible application profiles that serve to override global driver settings. When you run the corresponding executable file, the settings for the specific application are automatically activated. Some profiles may contain settings that cannot be changed by users. As a rule, this is adapting the driver for a specific application or eliminating compatibility problems. By default, only those applications that are installed on the system are displayed.

Specify settings for this program.

In this field you can change the settings for a specific application profile. The list of available settings is completely identical to the global parameters. The “Add” button is used to add your own application profiles. When you click it, a Windows Explorer window opens, with which you select the executable file of the application. After that, in the “Specify settings for this program” field, you can set personal settings for the application. The “Delete” button is used to delete user application profiles. Please note that you cannot delete/change initially existing application profiles using the driver; to do this you will have to use third-party utilities such as nHancer.

Setting up PhysX configuration

Allows you to enable or disable physics processing using NVIDIA PhysX technology on the graphics card, provided it is based on a G80 (GeForce 8X00) or newer GPU. Support is enabled by default; disabling it may be necessary when solving problems with applications that do not use PhysX correctly (for example, the game Mirror`s Edge without patches). If there is more than one NVIDIA GPU in the system, the user is given the opportunity to select the GPU on which physics processing will occur, unless SLI mode is used. You can find out more about the features of using NVIDIA PhysX in the special FAQ section of our website.

Additionally, starting with driver version 195.62, you can enable the display of the PhysX acceleration indicator in games. To do this, in the top menu “3D Options” check “Show PhysX visual indicator”. The acceleration status is displayed in the upper left corner of the image.